Semi-Conductor Laboratory (SCL) offers opportunity to academia to participate and contribute in conducting Research & Development (R&D) activities related to Micro-electronics with larger interest related to Space Science/ Technology/ Application. For taking-up such R&D by Academic Institutes/ Universities, financial support is provided through sponsoring approved Projects. This programme of Research Sponsored by ISRO is known as RESPOND. In special cases Research & Development Projects proposed by Non-academic R&D Laboratories can also be supported through this programme. For more detail please click the link RESPOND.

New developments in CMOS Process Technology at SCL

SCL has 180nm baseline CMOS Process Technology in its 8” wafer fab. The CMOS process is dual-doped single-poly 6-layer metal process. It also supports optional analog process modules, such as HVt, HRPOLY, MIM capacitor modules. The following research topics/areas of developments are proposed for process enhancements to enable the design & development of variety of ASICs in the current fab (High-voltage,  Rad-Hard-by-Design (RHBD), embedded memory, RF-design etc).

  1. Development of 1.8/5V Input/Output Interface Circuits (I/O) (Analog and Digital Pad Circuits with ESD protection) with better than 2000V ESD tolerance.

  2. RF-ASIC Design enablement in 180nm CMOS baseline process:

    1. Characterisation & RF-Model development for 1.8V MOSFETs of 180nm CMOS Process at SCL: The minimum-channel length of MOSFETs SCL process (180nm CMOS technology) has Unity Current Gain frequency, Ft ~55 GHz. The existing device models supported by the technology are valid up to baseband frequencies (one tenth of Ft of transistors) only. Development of accurate frequency dependant SPICE models for both n-channel & p-channel MOSFETs upto unity gain frequency of operation (in gigahertz range) is required. The models should be scalable across different sizes of transistors as allowed by the process design rules and cover the bias (1.8V), temperature (-55 to 125C) and frequency (DC to 55 GHz) range  of operations with better accuracy (<10% error) between the model to the measurements. In this work, SCL will support fabrication of specific test chip as proposed for the requirement and electrical characterization of fabricated test structures at different bias & temperatures regions as possible with existing characterization tools. RF-measurements & characterization, BSIM3v3 device model parameter extraction, model validation, SPICE documentation etc have be carried out.

    2. Design & development of RF-passives, Inductors, Capacitors, Varactors in the baseline process: Design, Simulation & Optimisation of passives based on RF-performance metrics (inductance or capacitance value, its variation with frequency, Q-factor, etc), test structure design & fabrication in the baseline process for performance characterization and modeling.

  3. SPICE Models development and qualification: SCL is working in the process development for SOI-CMOS technology & LDMOS devices. In this, development of MOSFET SPICE models for partially depleted MOSFETs & LDMOS devices is required. The developed models should be scalable over various sizes of transistors allowed in the process including the bias, temperature and RF-frequency range of operation with better accuracy <10% error.

  4. Design and development of embedded NVM: Single-time programmable or MTP memories or Flash EEPROM: Process design & simulation studies and optimization of the basic cell architectures for evaluation and qualification.

  5. High performance BJT or SiGe-HBT process integration: Process Flow design, growth & characterization of epitaxial layers, test chip of test structures of various design & process architectures, device DC and RF-characterisation, device models development for high-speed/RF-applications.

New developments in imaging at SCL

SCL has developed CCD visible imaging devices for space applications. New developments are being undertaken to enhance the current capability to cater to more advanced requirements of space and other scientific research applications. These include enhancement of the spectral range of the existing imagers as well as the incorporation of new features. New devices like large area photodiode detectors are also being developed for scientific imaging applications. Following new developments are being taken up:

The different CCD architectures developed in SCL include photodiode based linear imagers and photo-gate based area imager devices. In area imagers the quantum efficiency (QE) is low in the short wavelength region (<500 nm approximately) because of photon absorption in the polysilicon gate material. Enhancement of QE can be done through device architecture, use of anti-reflection coatings or other special materials.

  1. Device architecture for enhanced QE: Increase of QE especially in CCD devices in the short wavelength bands is done through the design of CCD architectures like Poly Hole and Open Pinned Phase (OPP).

  2. Anti-reflection coatings (ARC) for improved QE: Design of thin film coatings is another avenue for the improvement of QE of CCD or CMOS image sensors. These can be single or multi-layer coatings of silicon oxides, nitrides and oxy-nitrides as well as metal oxides.

  3. Use of transparent gates in CCD devices: One approach for improving the short wavelength quantum efficiency in CCD devices is through the replacement of the gate material of a CCD by a transparent conductor e.g., Indium Tin Oxide (ITO). Depending on the requirement, either the second or both polysilicon gate levels can be replaced.

  4. Back-Illuminated CCD and CMOS Image Sensors: The best solution for improving the quantum efficiency in any imaging device is to have the illumination from the back-side of the die. The benefit is more pronounced towards the short wavelength end of the visible spectrum. This will result in extension of the device spectral range to the near-UV region and improved performance in the mid-band region. This requires wafer thinning to various levels depending on the application and development of techniques for backside passivation of the wafer after wafer thinning for achieving good photo-response uniformity and low dark signal operation.

Apart from the above new technology developments, SCL is also entering into the areas of CMOS Image Sensors and the development of large area photodiode sensors for various imaging applications.