CMOS Process Feature


Baseline Technology Features   Analog Process Modules
1.8V Core CMOS   High-Vt (Low leakage current ~one order less)
1.8V or 3.3V I/O   Metal Insulator Metal capacitor: Single MIM (1 & 2fF/µm2) & stacked MIMs (2x)
Single poly & upto 6 Metal Layers with USG-BEOL   Deep N-Well (Isolated p-wells for substrate noise isolation)
23-34 Mask layers (depending on Metal Layers and Analog modules)   High resistance poly silicon resistor: HIPO (1kΩ/sq; 2kΩ/sq)
  Thick Last metal (2µm)
  5V-MOSFETs (Gox: 110A)
         
Salient Process Features

 

 

 

 

 

 

 


                                

8” p-type Silicon (1-2 Ω-cm)
Shallow Trench Isolation (STI)
Retrograde wells
Dual gate oxide (Nitrided gate oxide:
30A:1.8V & 70A:3.3V/110A:5V)
Dual gate poly (p+ doped for PMOS & n+ doped for NMOS)
Salicide (Cobalt Silicide for S/D & gate poly)
Tungsten(W) Fill contacts/Vias
Ti/TiN/AlCu/Ti/TiN metal interconnects
High density plasma oxide, USG (k=4.2) as Inter Metal Dilectric (IMD)
CMP (for STI, ILD/IMD, Tungsten Contacts/Vias
DUV (248nm) with Rule based OPC & MUV (365nm) lithography for critical & non-critical layers.