CMOS Process Feature

Baseline Technology Features   Salient Process Features
1.8V Core CMOS   8" p-type Ar-annealed Silicon Wafers (typically)
1.8V or 3.3V I/O   Shallow Trench Isolation (STI)
Single Poly  &  4-6 Metal Layers   Retrograde Wells
23-34 Mask Layers (depending on Circuit Complexity and Mixed-Signal / Analog Features)   Nitrided Gate Oxide (1.8V-CMOS)
      Gate Oxide (3.3 V-CMOS)
Analog Process Modules   Dual Gate Poly (p+ for PMOS & n+ for NMOS)
High Vt MOSFETs (Low leakage current ~one order less)   Selective Cobalt Salicidation ( for Source/Drain Diffusions & Gate Poly)
Metal-Insulator-Metal (MIM) Capacitor (1fF/Ám2)   Tungsten (W) Plugs for Contacts/Vias
Deep N-Well (Isolated p-Wells for Noise Isolation)   Ti/TiN/AlCu/Ti/TiN Metal Interconnects
High Resistance Polysilicon Resistor - HIPO (1k/sq)   High Density Plasma (HDP) Gap Fill Oxides for Inter Metal Dielectric (IMD)
Thick Last Metal (2Ám)   Chemical Mechanical Planarization (CMP) for STI-oxide, IMD & W-Plugs
Standard Cell library
Type Description
Standard Cells
1.8V- Standard Cell Library
(540 cells; height = 5.6 Ám)
Memory Cuts SP-SRAM : 10 sizes
DP-SRAM : 10 sizes
Via-Programmable ROM : 10 sizes
I/O Cells 1.8V & 1.8V/3.3V
(Designed to be used at a frequency up to 130MHz, on a maximum external load capacitance of 40pF and for a pin package inductance up to 20nH.)
1.8V Standard Cells for Logic Design
I/O Library Cells
SRAM and ROM Blocks/Cuts